Struct CacheParameter

pub struct CacheParameter {
    pub(crate) eax: u32,
    pub(crate) ebx: u32,
    pub(crate) ecx: u32,
    pub(crate) edx: u32,
}

Information about an individual cache in the hierarchy.

Platforms

🟡 AMD ✅ Intel

Fields

eax: u32

ebx: u32

ecx: u32

edx: u32

Implementations

impl CacheParameter

pub fn cache_type(&self) -> CacheType

Cache Type

Platforms

✅ AMD ✅ Intel

pub fn level(&self) -> u8

Cache Level (starts at 1)

Platforms

✅ AMD ✅ Intel

pub fn is_self_initializing(&self) -> bool

Self Initializing cache level (does not need SW initialization).

Platforms

✅ AMD ✅ Intel

pub fn is_fully_associative(&self) -> bool

Fully Associative cache

Platforms

✅ AMD ✅ Intel

pub fn max_cores_for_cache(&self) -> usize

Maximum number of addressable IDs for logical processors sharing this cache

Platforms

✅ AMD ✅ Intel

pub fn max_cores_for_package(&self) -> usize

Maximum number of addressable IDs for processor cores in the physical package

Platforms

❌ AMD ✅ Intel

pub fn coherency_line_size(&self) -> usize

System Coherency Line Size (Bits 11-00)

Platforms

✅ AMD ✅ Intel

pub fn physical_line_partitions(&self) -> usize

Physical Line partitions (Bits 21-12)

Platforms

✅ AMD ✅ Intel

pub fn associativity(&self) -> usize

Ways of associativity (Bits 31-22)

Platforms

✅ AMD ✅ Intel

pub fn sets(&self) -> usize

Number of Sets (Bits 31-00)

Platforms

✅ AMD ✅ Intel

pub fn is_write_back_invalidate(&self) -> bool

Write-Back Invalidate/Invalidate (Bit 0) False: WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this cache. True: WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing this cache.

Platforms

✅ AMD ✅ Intel

pub fn is_inclusive(&self) -> bool

Cache Inclusiveness (Bit 1) False: Cache is not inclusive of lower cache levels. True: Cache is inclusive of lower cache levels.

Platforms

✅ AMD ✅ Intel

pub fn has_complex_indexing(&self) -> bool

Complex Cache Indexing (Bit 2) False: Direct mapped cache. True: A complex function is used to index the cache, potentially using all address bits.

Platforms

❌ AMD ✅ Intel

Trait Implementations

impl Clone for CacheParameter

fn clone(&self) -> CacheParameter

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CacheParameter

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl PartialEq for CacheParameter

fn eq(&self, other: &CacheParameter) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for CacheParameter

impl Eq for CacheParameter

impl StructuralPartialEq for CacheParameter