ostd::arch::kernel::apic

Struct Icr

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pub struct Icr(u64);
Expand description

The inter-processor interrupt control register.

ICR is a 64-bit local APIC register that allows software running on the processor to specify and send IPIs to other processors in the system. To send an IPI, software must set up the ICR to indicate the type of IPI message to be sent and the destination processor or processors. (All fields of the ICR are read-write by software with the exception of the delivery status field, which is read-only.)

The act of writing to the low doubleword of the ICR causes the IPI to be sent. Therefore, in xapic mode, high doubleword of the ICR needs to be written first and then the low doubleword to ensure the correct interrupt is sent.

The ICR consists of the following fields:

  • Bit 0-7 Vector :The vector number of the interrupt being sent.
  • Bit 8-10 Delivery Mode :Specifies the type of IPI to be sent.
  • Bit 11 Destination Mode :Selects either physical or logical destination mode.
  • Bit 12 Delivery Status(RO) :Indicates the IPI delivery status.
  • Bit 13 Reserved
  • Bit 14 Level :Only set 1 for the INIT level de-assert delivery mode.
  • Bit 15 Trigger Mode :Selects level or edge trigger mode.
  • Bit 16-17 Reserved
  • Bit 18-19 Destination Shorthand :Indicates destination set.
  • Bit 20-55 Reserved
  • Bit 56-63 Destination Field :Specifies the target processor or processors.

Tuple Fields§

§0: u64

Implementations§

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impl Icr

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pub fn new( destination: ApicId, destination_shorthand: DestinationShorthand, trigger_mode: TriggerMode, level: Level, delivery_status: DeliveryStatus, destination_mode: DestinationMode, delivery_mode: DeliveryMode, vector: u8, ) -> Self

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pub fn lower(&self) -> u32

Returns the lower 32 bits of the ICR.

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pub fn upper(&self) -> u32

Returns the higher 32 bits of the ICR.

Auto Trait Implementations§

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impl Freeze for Icr

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impl RefUnwindSafe for Icr

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impl Send for Icr

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impl Sync for Icr

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impl Unpin for Icr

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impl UnwindSafe for Icr

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